Z80180 Datasheet, PDF (190/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
175
TST (HL) - Test Memory
The contents of memory pointed to by HL are ANDed with the accumulator
(A) and the status flags are updated. The memory contents and accumulator
are not changed (non-destructive AND).
INO g, (m) - Input, Immediate I/O address
The contents of immediately specified 8-bit I/O address are input into the
specified register. When I/O is accessed, 00H is output in high-order bits
of the address automatically.
OUTO (m), g - Output, Immediate I/O address
The contents of the specified register are output to the immediately
specified 8-bit I/O address. When I/O is accessed, 00H is output in high-
order bits of the address automatically.
CPU REGISTERS
The Z80180 CPU registers consist of Register Set GR, Register Set GR'
and Special Registers.
The Register Set GR consists of 8-bit Accumulator (A), 8-bit Flag Register
(F), and three General Purpose Registers (BC, DE, and HL) which may be
treated as 16-bit registers (BC, DE, and HL) or as individual 8-bit registers
(B, C, D, E, H, and L) depending on the instruction to be executed. The
Register Set GR' is alternate register set of Register Set GR and also contains
Accumulator (A'), Flag Register (F') and three General Purpose Registers
(BC', DE', and HL'). While the alternate Register Set GR' contents are not
directly accessible, the contents can be programmably exchanged at high
speed with those of Register Set GR.
The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit
R Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack
Pointer (SP), and 16-bit Program Counter (PC)
UM005001-ZMP0400