Z80180 Datasheet, PDF (36/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
21
Phi
A0–A19
Wait States (TW) are inserted as previously described for Op Code fetch
cycles. Figure 11 illustrates the read/write timing without Wait States
(Tw), while Figure 12 illustrates read/write timing with Wait States (TW).
Read Cycle
T1
T2
T3
Write Cycle
T1
T2
T3
T1
Memory address
Memory address
D0–D7
WAIT
MREQ
RD
WR
Read data
Write data
Figure 11. Memory Read/Write (without Wait State) Timing Diagram
UM005001-ZMP0400