Z80180 Datasheet, PDF (189/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
174
MLT- Multiply
The MLT performs unsigned multiplication on two 8-bit numbers yielding a
16-bit result. MLT may specify BC, DE, HL, or SP registers. The 8-bit
operands are loaded into each half of the 16-bit register and the 16-bit result
is returned in that register.
OTIM, OTIMR, OTDM, OTDMR - Block I/O
The contents of memory pointed to by HL is output to the I/O address in (C).
The memory address (HL) and I/O address (C) are incremented in OTIM
and OTIMR and decremented in OTDM and OTDMR, respectively. The B
register is decremented. The OTIMR and OTDMR variants repeat the above
sequence until register B is decremented to 0. Since the I/O address (C) is
automatically incremented or decremented, these instructions are useful for
block I/O (such as Z80180 on-chip I/O) initialization. When I/O is accessed,
00H is output in high-order bits of address automatically.
TSTIO m - Test I/O Port
The contents of the I/O port addressed by C are ANDed with immediately
specified 8-bit data and the status flags are updated. The I/O port contents
are not written (non-destructive AND). When I/O is accessed, 00H is
output in higher bits of address automatically.
TST g - Test Register
Perform an AND instruction on the contents of the specified register with
the accumulator (A) and the status flags are updated. The accumulator
and specified register are not changed (non-destructive AND).
TST m - Test Immediate
Perform an AND instruction on the contents of the immediately specified
8-bit data with the accumulator (A) and the status flags are updated. The
accumulator is not changed (non-destructive AND).
UM005001-ZMP0400