Z80180 Datasheet, PDF (231/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
215
Table 38. Arithmetic and Logical Instructions (8-bit) (Continued)
Flags
Operation
Name
Mnemonics
Addressing
Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation
764 2 10
S Z H P/V N C
SUBC
TEST
XOR
SBC A,g
10 011 g
SBC A,(HL) 10 011 110
SBC A,m
11 011 110 S
<m>
SBC A,(IX + d) 11 011 101
10 011 110
<d>
SBC A,(IY + d) 11 111 101
10 011 110
<d>
TST g**
11 101 101
00 g 100
TST {HL)**
11101101
00 110 100
TST m**
11 101 101 S
01 100 100
<m>
XOR g
10 101 g
XOR (HL)
10 101 110
XOR m
11 101 110 S
<m>
XOR (IX + d) 11 011 101
10 101 110
<d>
S
D
SD
D
S
D
1
4
1
6
2
6
Ar-gr-c→ Ar
Ar-(HL)_M-c→ Ar
Ar-m-c→ Ar
↑↑↑V S↑
↑↑↑V S↑
↑↑↑V S↑
3
14 Ar-(IX + d)_M-c→ Ar ↑ ↑ ↑ V S ↑
S
D
3
14 Ar-(IY + d)_M-c→ Ar ↑ ↑ ↑ V S ↑
S
S
2
7
Ar•gr
2
10 Ar•(HL)_M
3
9
Ar•m
↑↑S P RR
↑↑S P RR
↑↑S P RR
S
D
SD
D
S
D
1
4
1
6
2
6
Ar⊕ + gr→ Ar
Ar⊕ + (HL)_M→ Ar
Ar⊕ + m→ Ar
↑↑RP RR
↑↑RP RR
↑↑RP RR
3
14 Ar⊕ + (IX + d))_M→ Ar ↑ ↑ R P R R
UM005001-ZMP0400