Z80180 Datasheet, PDF (68/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
53
CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only)
Bit
7
6
5
4
3
Bit/Field
Clock
Divide
STAND
BY/
IDLE
Enable
BREXT
LNPHI
STAND
BY/
IDLE
Enable
R/W
R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
2
LNIO
R/W
0
1
0
LNCPU LNAD/
CTL DATA
R/W R/W
0
0
Bit
Position Bit/Field
R/W Value Description
7
Clock
R/W 0 XTAL/2
Divide
1 XTAL/1
6
STANDBY R/W
In conjunction with Bit 3
/IDLE Mode
00 No STANDBY
01 IDLE after SLEEP
10 STANDBY after SLEEP
11 STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
5
BREXT
R/W 0 Ignore BUSREQ in STANDBY/IDLE
1 STANDBY/IDLE exit on BUSREQ
4
LNPHI
R/W 0 Standard Drive
1 33% Drive on EXTPHI Clock
3
STANDBY R/W
In conjunction with Bit 6
/IDLE Mode
00 No STANDBY
01 IDLE after SLEEP
10 STANDBY after SLEEP
11 STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
UM005001-ZMP0400