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Z80180 Datasheet, PDF (48/326 Pages) Zilog, Inc. – Z8018x Family MPU | |||
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Z 8018x Fam ily
M PU Us e r M anual
33
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Phi
INT1, NMI
HALT Op Code
Fetch Cycle
T1
T3
T1
HALT mode
T2
T3
Interrupt
acknowledge cycle
T1
T2
A0âA19 HALT Op Code address
HALT Op Code address + 1
HALT
M1
MREQ
RD
Figure 20. HALT Timing Diagram
SLEEP Mode
SLEEP mode is entered by execution of the 2-byte SLP instruction.
SLEEP mode contains the following characteristics:
⢠The internal CPU clock stops, reducing power consumption
⢠The internal crystal oscillator does not stop
⢠Internal and external interrupt inputs can be received
⢠DRAM refresh cycles stop
⢠I/O operations using on-chip peripherals continue
⢠The internal DMAC stop
⢠BUSREQ can be received and acknowledged
⢠Address outputs go High and all other control signal outputs become
inactive High
UM005001-ZMP0400
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