Z80180 Datasheet, PDF (104/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
89
Table 11. DRAM Refresh Intervals
Insertion
CYC1 CYC0 Interval
0
0
10 states
0
1
20 states
1
0
40 states
1
1
80 states
* Calculated interval
10 MHz
(1.0 µs)*
(2.0 µs)*
(4.0 µs)*
(8.0 µs)*
Time Interval
8 MHz
(1.25 µs)*
(2.5 µs)*
(5.0 µs)*
(10.0 µs)*
6 MHz
1.66 µs
3.3 µs
6.8 µs
13.3 µs
4 MHz
2.5 µs
5.0 µs
10.0 µs
20.0 µs
2.5 MHz
4.0 µs
8.0 µs
16.0 µs
32.0 µs
Refresh Control And RESET
After RESET, based on the initialized value of RCR, refresh cycles occur
with an interval of ten clock cycles and are three clock cycles in duration.
Dynamic Ram Refresh Operation Notes
1. Refresh Cycle insertion is stopped when the CPU is in the following
states:
– During RESET
– When the bus is released in response to BUSREQ
– During SLEEP mode
– During Wait States
2. Refresh cycles are suppressed when the bus is released in response to
BUSREQ. However, the refresh timer continues to operate. Thus, the
time at which the first refresh cycle occurs after the Z8X180 re-
acquires the bus depends on the refresh timer and has no timing
relationship with the bus exchange.
UM005001-ZMP0400