Z80180 Datasheet, PDF (84/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
69
If IEF1 is 0, all maskable interrupts are disabled. IEF1 can be reset to 0 by
the DI (Disable Interrupts) instruction and set to 1 by the El (Enable
Interrupts) instruction.
The purpose of IEF2 is to correctly manage the occurrence of NMI.
During NMI, the prior interrupt reception state is saved and all maskable
interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1
cleared to 0). At the end of the NMI interrupt service routine, execution of
the RETN (Return from Non-maskable Interrupt) automatically restores
the interrupt receiving state (by copying IEF2 to IEF1) prior to the
occurrence of NMI.
Table 8 describes how the IEF2 state can be reflected in the P/V bit of the
CPU Status Register by executing LD A, I or LD A, R instructions.
Table 8. State of IEF1 and IEF2
CPU
Operation
IEF1
IEF2
REMARKS
RESET
0
0
Inhibits the interrupt except NMI
and TRAP.
NMI
0
IEF1
Copies the contents of IEF1 to
IEF2
RETN
IEF2
not affected Returns from the NMI service
routine.
Interrupt except 0
0
Inhibits the interrupt except NMI
NMI end TRAP
end TRAP
RETI
not affected not affected
TRAP
not affected not affected
EI
1
1
UM005001-ZMP0400