Z80180 Datasheet, PDF (93/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
78
Phi
INT0
A0–A19
M1
MREQ
IORQ
RD
WR
D0–D7
ST
Last MC
INT0 Acknowledge Cycle
PC is pushed onto stack
Op Code Fetch Cycle
T1 T2 TW* TW* T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
PC
SP-1
SP-2
0038H
PCH
PCL
*Two Wait States are automatically inserted
Figure 38. INT0 Mode 1 Timing
INT0 Mode 2
This method determines the restart address by reading the contents of a
table residing in memory. The vector table consists of up to 128 two-byte
restart addresses stored in low byte, high byte order.
UM005001-ZMP0400