Z80180 Datasheet, PDF (112/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
97
Bit
Position Bit/Field R/W
0
DME R
Value Description
DMA Main Enable — A DMA operation is only enabled
when its DE bit DE0 for channel 0, DE1 for channel 1)
and the DME bit are set to 1.
When NMI occurs, DME is reset to 0, thus disabling
DMA activity during the NMI interrupt service
routine. To restart DMA, DE0 and/or DE1 must be
written with 1 (even if the contents are already 1).
This action automatically sets DME to 1, allowing
DMA operations to continue. DME cannot be
directly written. It is cleared to 0 by NMI or
indirectly set to 1 by setting DE0 and/or DE1 to
1.DME is cleared to 0 during RESET.
DMA Mode Register (DMODE)
DMODE is used to set the addressing and transfer mode for channel 0.
DMA Mode Register (DMODE: 31H)
Bit
7
6
5
4
3
2
1
0
Bit/Field
?
DM1 DM0 SM1 SM0 MMOD ?
R/W
?
R/W R/W R/W R/W R/W
?
Reset
?
0
0
0
0
0
?
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
5–4
DM1:0 R/W
Value Description
Destination Mode Channel 0 — Specifies whether the
destination for channel 0 transfers is memory, I/O or
memory mapped I/O and the corresponding address
modifier. Reference Table 12.
UM005001-ZMP0400