Z80180 Datasheet, PDF (179/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
164
Timer Data
Reg. = 0001H
Phi
Timer Data
Reg. = 0000H
TOUT
Figure 65. Timer Output Timing Diagram
PRT Interrupts
The PRT interrupt request circuit is illustrated in Figure 66.
IEF1
TIF1
TIE1
PRT1 Interrupt
Request
TIF0
TIE0
PRT0 Interrupt
Request
Figure 66. PRT Interrupt Request Generation
PRT and RESET
During RESET, the bits in TCR are initialized as defined in the TCR
register description. Down counting is stopped and the TMDR and RLDR
registers are initialized to FFFFH. The A18/TOUT pin reverts to the
address output function.
UM005001-ZMP0400