Z80180 Datasheet, PDF (127/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
112
4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in
DCNTL.
5. Enable or disable DMA termination interrupt with the DIE1 bit in
DSTAT.
6. Program DE1 = 1 (with DWE1 = 0 in the same access) in DSTAT
and the DMA operation with the external I/O device begins using the
external DREQ1 input and TEND1 output.
DMA Bus Timing
When memory (and memory mapped I/O) is specified as a source or
destination, MREQ goes Low during the memory access. When I/O is
specified as a source or destination, IORQ goes Low during the I/O access.
When I/O (and memory mapped I/O) is specified as a source or
destination, the DMA timing is controlled by the external DREQ input
and the TEND output indicates DMA termination
Note: External I/O devices may not overlap addresses with internal I/O
and control registers, even using DMA.
For I/O accesses, one Wait State is automatically inserted. Additional
Wait States can be inserted by programming the on-chip wait state
generator or using the external WAIT input.
Note: For memory mapped I/O accesses, this automatic I/O Wait State
is not inserted.
For memory to memory transfers (channel 0 only), the external DREQ0
input is ignored. Automatic DMA timing is programmed as either
BURST or CYCLE STEAL.
When a DMA memory address carry/borrow between bits A15 and A16
of the address bus occurs (crossing 64KB boundaries), the minimum bus
UM005001-ZMP0400