Z80180 Datasheet, PDF (151/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
136
Bit
Position Bit/Field R/W Value Description
0
Send
R/W 0 Normal Xmit
Break
1 Drive TXA Low
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
Bit/Field
RDRF
Int
Inhibit
Reserved
X1 Bit
Clk
ASCI1
BRG1
Mode
R/W
R/W
?
R/W R/W
Reset
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
2
Break
Feature
Enable
R/W
0
1
Break
Detect
(RO)
R/W
0
0
Send
Break
R/W
0
Bit
Position Bit/Field R/W Value Description
7
RDRF R/W 0 RDRF Interrupt Inhibit On
Interrupt
1 RDRF Interrupt Inhibit Off
Inhibit
6–5
Reserved ?
0 Reserved. Must be 0
4
X1 Bit R/W 0 CKA1 /16 or /64
Clk
1 CKA1 is bit clock
ASCI1
3
BRG1
R/W
0 As S180
Mode
1 Enable 16-bit BRG counter
UM005001-ZMP0400