Z80180 Datasheet, PDF (64/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
49
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Address
Register
Timer Data Register Ch 0 L
Data Register Ch 0 H
Reload Register Ch 0 L
Reload Register Ch 0 H
Timer Control Register
Reserved
Data Register Ch 1 L
Data Register Ch 1 H
Reload Register Ch 1 L
Reload Register Ch 1 H
Others Free Running Counter
Reserved
Mnemonic Binary
Hex
TMDR0L
TMDR0H
RLDR0L
RLDR0H
TCR
TMDR1L
TMDR1H
RLDR1L
RLDR1H
FRC
XX001100 0CH
XX001101 0DH
XX001110 0EH
XX001111 0FH
XX010000 10H
XX010001 11H
XX010100 14H
XX010101 15H
XX010110 16H
XX010111 17H
XX011000 18H
XX011001 19H
Page
159
159
159
159
161
160
160
160
160
172
Clock Multiplier Register
CPU Control Register
CMR
CCR
XX011111 1DH
XX011110 1EH 52
XX011111 1FH 53
UM005001-ZMP0400