Z80180 Datasheet, PDF (184/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
169
Table 25. Z8X180 Operating Frequencies
Item
Clock
Frequency
Co
Rs
CL1, CL2
4MHz
4MHz < f ≤12MHz 12MHz < f ≤33MHz
< 7 pF
<60Ω
< 7 pF
<60Ω
< 7 pF
<60Ω
10 to 22 pF ± 10% 10 to 22 pF ±10% 10 to 22 pF ± 10%
If an external clock input is used instead of a crystal, the waveform (twice
the clock rate) must exhibit a 50% ±10% duty cycle.
Note:
The minimum clock input High voltage level is V_CC –0.6V. The
external clock input is connected to the EXTAL pin, while the
XTAL pin is left open. Figure 70 depicts the external clock
interface.
EXTAL ³
XTAL ² Open
External Clock Input
Figure 70. External Clock Interface
Figure 71 illustrates the Z8X180 clock generator circuit while Figures 72
and 72 specify circuit board design rules.
UM005001-ZMP0400