Z80180 Datasheet, PDF (297/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
281
Operating Modes Summary
REQUEST ACCEPTANCES IN EACH OPERATING MODE
Table 53. Request Acceptances in Each Operating Mode
Current Normal
Status Operation
(CPU mode
and IOSTOP
Request
Mode)
Refresh
WAIT State Cycle
Interrupt
BUS
Acknowledge
RELEASE SLEEP
Cycle
DMA Cycle Mode
Mode
SYSTEM
STOP
Mode
WAIT
Acceptable
Acceptable Not
Acceptable
acceptable
Acceptable Not
Not
Not
acceptable acceptable acceptable
Refresh Request Refresh cycle Not
Request of Refresh begins at the acceptable
by the on-chip end of Machine
Refresh Controller Cycle (MC)
Not
acceptable
Refresh cycle
begins at the
end MC
Refresh cycle Not
Not
Not
begins at the acceptable acceptable acceptable
end of MC
DREQ0
DREQ1
DMA cycle
begins at the
end of MC
DMA cycle
begins at the
end of MC
Acceptable Acceptable
Refresh cycle DMA cycle
precedes. begins at the
DMA cycle end of MC.
begins at the
end of one
MC
Acceptable
Refer to
“DMA
Controller”
for details.
Acceptable Not
*After BUS acceptable
RELEASE
cycle, DMA
cycle begins
at the end of
one MC
Not
acceptable
BUSREQ
Bus is released Not
at the end of acceptable
MC
Not
acceptable
Bus is released
at the end of
MC
Bus is
Continue
released at the BUS
end of MC RELEASE
mode
Acceptable Acceptable
Interrupt INT0,
INT1,
1NT2
Accepted after
executing the
current
instruction.
Accepted
after
executing the
current
instruction
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable Acceptable
Return from Return from
SLEEP
SYSTEM
mode to STOP mode
normal
to normal
operation. operation
UM005001-ZMP0400