M16C62P_06 Datasheet, PDF (98/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Sub-clock
generating circuit
XCIN
XCOUT
CM04
CM21
CM10=1(stop mode)
WAIT instruction
SQ
R
XIN XOUT
CM05
Main
clock
Main clock
generating circuit
SQ
R
RESET
Software reset
NMI
Interrupt request level judgment output
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
PCLK0, PCLK1: Bits in PCLKR register
CM21, CM27 : Bits in CM2 register
Sub-clock
On-chip
oscillator
On-chip
oscillator
clock
Oscillation
stop,
re-oscillation
detection
circuit
PLL
frequency
synthesizer
PLL
1 ^clock
0
CM11
CM21=1
CM21=0
I/O ports
CM01 to CM00=00b
PM01 to PM00=00b, CM01 to CM00=01b
PM01 to PM00=00b, CM01 to CM00=10b
fC32
1/32
f1
PCLK0=1
f2
PCLK0=0
fC
f8
CLKOUT
PM01 to PM00=00b,
CM01 to CM00=11b
f32
fAD
f1SIO
f2SIO
PCLK1=1
PCLK1=0
f8SIO
eb c
a _Divider d
f32SIO
CM07=0
D4INT clock
CPU clock
fC
CM07=1
BCLK
CM02
e
b
c
a
1/2
1/2
1/2
1/2
1/2
1/32
1/2
1/4
1/8
1/16
CM06=1
CM06=0
CM17 to CM16=10b
CM06=0
CM17 to CM16=11b
d
CM06=0
CM17 to CM16=01b
CM06=0
CM17 to CM16=00b
Details of divider
Oscillation Stop, Re-Oscillation Detection Circuit
Main
clock
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
Charge,
discharge
circuit
CM27=0
CM27=1
Reset
generating
circuit
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Oscillation stop
detection reset
Oscillation stop
detection reset
CM21 switch signal
PLL Frequency Synthesizer
Main clock
Programmable
counter
Phase
compar
ator
Figure 10.1 Clock Generation Circuit
Rev.2.41 Jan 10, 2006 Page 83 of 390
REJ09B0185-0241
Charge
pump
1/2
Voltage
control
oscillator
(VCO)
Internal lowpass
filter
PLL Clock