M16C62P_06 Datasheet, PDF (358/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
CSi
ADi
BHE
ALE
RD
td(BCLK-CS)
30ns.max
td(BCLK-AD)
30ns.max
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-RD)
30ns.max
DBi
Hi-Z
tac2(RD-DB)
(3.5 × tcyc-60)ns.max
Write timing
tcyc
BCLK
CSi
ADi
BHE
ALE
td(BCLK-CS)
30ns.max
td(BCLK-AD)
30ns.max
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
WR, WRL
WRH
DBi
td(BCLK-WR)
30ns.max
td(BCLK-DB)
40ns.max
Hi-Z
tcyc=
1
f(BCLK)
td(DB-WR)
(2.5 × tcyc-40)ns.min
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 23.19 Timing Diagram (7)
Rev.2.41 Jan 10, 2006 Page 343 of 390
REJ09B0185-0241
VCC1 = VCC2 = 3V
th(BCLK-CS)
4ns.min
th(BCLK-AD)
4ns.min
th(RD-AD)
0ns.min
th(BCLK-RD)
0ns.min
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(BCLK-CS)
4ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5 × tcyc-10)ns.min
th(BCLK-WR)
0ns.min
th(BCLK-DB)
4ns.min
th(WR-DB)
(0.5 × tcyc-10)ns.min