M16C62P_06 Datasheet, PDF (334/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.29 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
Standard
Unit
Min.
Max.
25
ns
4
ns
(NOTE 1)
ns
(NOTE 1)
ns
25
ns
4
ns
(NOTE 1)
ns
(NOTE 1)
ns
25
ns
0
ns
25
ns
See
0
Figure 23.2
ns
40
ns
4
ns
(NOTE 2)
ns
(NOTE 1)
ns
40
ns
15
ns
−4
ns
(NOTE 3)
ns
(NOTE 4)
ns
0
ns
0
ns
8
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
f-0--(^{--.B-5---C-x----1L---0-K--9---}) ^{– 10[ns]}
2. Calculated according to the BCLK frequency as follows:
(_---n-----–_{----0----.-5----})_{---x---1---0----9--}
f(BCLK)
–
40
[
ns
]
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
-0----.-5----x----1---0---9---
f(BCLK)
–
25 [
ns
]
4. Calculated according to the BCLK frequency as follows:
f-0--(^{--.B-5---C-x----1L---0-K--9---}) ^{– 15[ns]}
Rev.2.41 Jan 10, 2006 Page 319 of 390
REJ09B0185-0241