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M16C62P_06 Datasheet, PDF (407/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES
REVISION HISTORY
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Rev.
Date
Page
88
96
99
100
103
104
105
109
115
117
117
122
124
128
128
130
132
134
137
146
163
164,
165
169
170
171
179
184
187
203
205
206
207
Description
Summary
Figure 1.11.9 is partly revised.
WDTS Register in Figure 1.12.2 is partly revised.
Figure 1.13.2 is partly revised.
Figure 1.13.3 is partly revised.
Figure 1.13.5 is partly revised.
Table 1.13.3 is partly revised.
Explanation of “DMA Enable” is partly revised.
Figure 1.14.3 is partly revised.
Table 1.14.5 is partly revised.
Explanation of “Counter Initialization by Two-Phase Pulse Signal
Processing” is partly revised.
Figure 1.14.10 is partly revised.
Figure 1.14.14 is partly revised.
Figure 1.14.15 is partly revised.
Figure 1.15.3 is partly revised.
Figure 1.15.7 is partly revised.
Figure 1.15.8 is partly revised.
Figure 1.16.1 is partly revised.
Figure 1.16.3 is partly revised.
Note 7 is added to TAi, TAi1 Register in Figure 1.16.5.
Figure 1.16.8 is partly revised.
UiSMR2 Register in Figure 1.17.7 is partly revised.
Figure 1.20.1 is partly revised.
Table 1.20.2 and Table 1.20.3 are partly revised.
Figure 1.20.4 is partly revised.
Explanation of “Arbitration” is partly revised.
Explanation of “Transfer Clock” is partly revised.
Explanation of “ACK and NACK” is partly revised.
Explanation of “Special Mode 4 (SIM Mode)” is partly revised.
Table 1.20.9 is partly revised.
Figure 1.21.1 is partly revised.
Figure 1.21.4 is partly revised.
Explanation of “External Operation Amp Connection Mode” is partly
revised.
Explanation of “Caution of Using A/D Converter” is partly revised.
Figure 1.22.11 is partly revised
Table 1.23.1 is partly revised.
Figure 1.23.3 is partly revised.
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