M16C62P_06 Datasheet, PDF (128/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.5.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable
interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
12.5.2 IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (=
interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
12.5.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 12.3 shows the Settings of Interrupt Priority Levels and Table 12.4 shows the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is accepted:
• I flag = 1
• IR bit = 1
• interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 12.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 Bits
Interrupt Priority
Level
000b
Level 0 (interrupt disabled)
Priority
Order
−
001b
Level 1
Low
010b
Level 2
011b
Level 3
100b
Level 4
101b
Level 5
110b
Level 6
111b
Level 7
High
Table 12.4Interrupt Priority Levels Enabled by IPL
IPL
000b
001b
010b
011b
100b
101b
110b
111b
Enabled Interrupt Priority Levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Rev.2.41 Jan 10, 2006 Page 113 of 390
REJ09B0185-0241