M16C62P_06 Datasheet, PDF (171/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
15.2 Timer B
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer B1.
[Precautions when using TimerB2]
• Event Counter Mode
• Pulse Period/Pulse Width
Measurement Mode
The external input signals cannot be counted. Set the TCK1 bit in the TB1MR
register to “1” when using the Event Counter Mode.
This mode cannot be used.
Figure 15.16 shows a Timer B Block Diagram. Figures 15.17 and 15.18 show registers related to the Timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer Mode:
The timer counts an internal count source.
• Event Counter Mode:
The timer counts pulses from an external device or overflows or
underflows of other timers.
• Pulse Period/Pulse Width Measurement Mode:
The timer measures pulse period or pulse width of an external signal.
High-order Bits of Data Bus
Select Clock Source
TCK1 to TCK0
f1 or f2 ⁰⁰
f8 ⁰¹
10
f32
fC32 ¹¹
00: Timer
10: Pulse Period and Pulse
Width Measurement
TMOD1 to TMOD0
TCK1
TBj Overflow
(Note 1, 2)
1
01:
Event Counter
Low-order Bits of Data Bus
8 low-order bits
Reload Register
8 high-
order bits
TBiS
Counter
TBiIN
Polarity Switching
0
and Edge Pulse
Counter Reset Circuit
i=0 to 5
NOTES :
1. Overflows or underflows.
2. j=i-1, however, j=2 when i=0 j=5 when i=3
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register
TBiS : Bits in the TABSR and the TBSR register
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Address
0391h - 0390h
0393h - 0392h
0395h - 0394h
0351h - 0350h
0353h - 0352h
0355h - 0354h
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 15.16 Timer B Block Diagram
Rev.2.41 Jan 10, 2006 Page 156 of 390
REJ09B0185-0241