M16C62P_06 Datasheet, PDF (127/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
INTi (0 to 5) Interrupt Control Register ⁽²⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
INT3IC ⁽⁴⁾
0044h
XX00X000b
S4IC/INT5IC
0048h
XX00X000b
S3IC/INT4IC
0049h
XX00X000b
INT0IC to INT2IC
005Dh to 005Fh
XX00X000b
Bit Symbol
Bit Name
Function
RW
Interrupt Priority Level Select Bit
b2 b1 b0
ILVL0
0 0 0 : Level 0 (interrupt disabled)
RW
0 0 1 : Level 1
0 1 0 : Level 2
ILVL1
0 1 1 : Level 3
1 0 0 : Level 4
RW
1 0 1 : Level 5
ILVL2
1 1 0 : Level 6
1 1 1 : Level 7
RW
Interrupt Request Bit
IR
0: Interrupt not requested
1: Interrupt requested
RW⁽¹⁾
Polarity Select Bit
POL
0 : Selects falling edge ^{(3, 5)}
1 : Selects rising edge
RW
—
Reserved Bit
Set to “0”
(b5)
RW
—
Nothing is assigned. When w rite, set to “0”.
(b7-b6) When read, their contents are indeterminate.
—
NOTES :
1. This bit can only be reset by w riting “0” (Do not w rite “1”).
2. To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
3. If the IFSRi bit (i = 0 to 5) in the IFSR register are “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
edge).
4. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the LVL2 to
ILVL0
5. Set the POL bit in the S3IC or S4IC register to “0” (falling edge) w hen the IFSR6 bit in the IFSR register = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 12.4 Interrupt Control Registers (2)
Rev.2.41 Jan 10, 2006 Page 112 of 390
REJ09B0185-0241