M16C62P_06 Datasheet, PDF (194/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Main clock, PLL clock, or on-chip oscillator clock
1/2 ^f2SIO
f1SIO
0 ^PCLK1
1
f1SIO or f2SIO
1/8
f8SIO
(UART2)
1/4
f32SIO
RXD2
RXD polarity reversing
circuit
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 to CLK0 _CKDIR
00
Internal
01
0
10
1
External
U2BRG
register
1 / (n2+1)
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock synchronous
type
001
Reception
control circuit
UART transmission
1/16 _{010, 100, 101, 110}
Clock synchronous
type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
0
1/2
Receive
clock
Transmit
clock
1
CLK2
CTS2 /
RTS2
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
Clock synchronous type ^{(when external clock is selected) CKDIR}
(when internal clock is selected)
CTS/RTS disabled
CTS/RTS selected
RTS2
1
CRS 0
CTS/RTS disabled
0
CTS2
1 _CRD
VSS
n2: Values set to the U2BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
NOTES :
1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Transmit/
receive
unit
Figure 17.3 UART2 Block Diagram
TXD
polarity
reversing
circuit ⁽¹⁾
TXD2
Rev.2.41 Jan 10, 2006 Page 179 of 390
REJ09B0185-0241