M16C62P_06 Datasheet, PDF (403/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 2. Difference between M16C/62P and M16C/30P
Appendix Table 2.2 Function Difference (1)⁽¹⁾
Item
Timers A, B count
source
Timer A two-phase
pulse signal
processing
Timer functions for
three-phase motor
control
Serial I/O
(UART0 to UART2)
UART0 to UART2,
SI/O3, SI/O4 count
source
M16C/62P
Selectable: f1, f2, f8, f32, fC32
Function Z-phase (counter reset) input
M16C/62A
Selectable: f1, f8, f32, fC32
No function Z-phase (counter reset) input
Function protect by protect register
Count source is selected:
f1, f2, f8, f32, fC32
Dead time timer count source is selected:
f1, f1 divided by 2, f2, f2 divided by 2
Three-phase output forcible shutoff function
based on NMI input is available, output
polarity change, carrier wave phase
detection.
(UART, clock synchronous, I²C bus, IEBus)
x3
Select from f1SIO, f2SIO, f8SIO, f32SIO
Function protect by protect register
Count source is selected:
f1, f8, f32, fC32
Dead time timer count source is fixed at f1
divided by 2
(UART, clock synchronous) x 2
(UART, clock synchronous, I²C bus, IEBus)
x1
Select from f1, f8, f32
Serial I/O RTS timing
UART0 to UART2
Overrun Error
Generation Timing
Assert low when receive buffer is read
This error occurs if the serial I/O started
receiving the next data before reading the
UiRB register (i=0 to 2) and received the 7
th bit of the next data (clock synchronous)
This error occurs if the serial I/O started
receiving the next data before reading the
UiRB register and received the bit one
before the last stop bit of the next data
(UART)
Assert low when reception is completed
This error occurs when the next data is
ready before contents of UARTi receive
buffer register are read out
CTS/RTS separate
function
UART2 data transmit
timing
Serial I/O sleep
function
Serial I/O I²C mode
Serial I/O I²C mode
SDA delay
SI/O3, SI/O4 clock
polarity
A/D Converter
A/D converter
operation clock
A/D Converter Input Pin
Have
After data was written, transfer starts at the
2nd BRG overflow timing
(same as UART0 and UART1)
None
Start condition, stop condition:
Auto-generationable
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Selectable
10 bits X 8 channels
Expandable up to 26 channels
Selectable: fAD, fAD divided by 2, 3, 4,
6, 12
Select from ports P0, P2, P10
None
After data was written, transfer starts at the
1st BRG overflow timing
(Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
Have
Start condition, stop condition:
Not auto-generationable
Analog or digital delay is selected as SDA
delay
SDA digital delay count source: 1/ f(XIN)
Fixed
10 bits X 8 channels
Expandable up to 10 channels
Selectable: fAD, fAD/2, fAD/4
Fixed at port P10
NOTES:
1. About the details and the electric characteristics, refer to hardware manual.
Rev.2.41 Jan 10, 2006 Page 388 of 390
REJ09B0185-0241