M16C62P_06 Datasheet, PDF (360/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
td(BCLK-CS)
40ns.max
CSi
ADi
/DBi
ADi
td(AD-ALE)
(0.5×tcyc-40)ns.min
Address
td(BCLK-AD)
40ns.max
td(AD-RD)
0ns.min
th(ALE-AD)
(0.5×tcyc-15)ns.min
tdZ(RD-AD)
8ns.max
tac3(RD-DB)
(2.5×tcyc-60)ns.max
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
ALE
RD
td(BCLK-RD)
40ns.max
VCC1=VCC2=3V
th(RD-CS)
(0.5×tcyc-10)ns.min
th(BCLK-CS)
6ns.min
Data input
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(BCLK-AD)
4ns.min
th(RD-AD)
(0.5×tcyc-10)ns.min
th(BCLK-RD)
0ns.min
Write timing
tcyc
BCLK
CSi
td(BCLK-CS)
40ns.max
ADi
/DBi
Address
td(AD-ALE)
(0.5×tcyc-40)ns.min
td(BCLK-DB)
50ns.max
ADi
BHE
(No multiplex)
td(BCLK-AD)
40ns.max
td(BCLK-ALE)
40ns.max
ALE
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
Data output
td(DB-WR)
(2.5×tcyc-50)ns.min
WR, WRL
WRH
td(BCLK-WR)
40ns.max
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 23.21 Timing Diagram (9)
Rev.2.41 Jan 10, 2006 Page 345 of 390
REJ09B0185-0241
th(WR-CS)
(0.5×tcyc-10)ns.min
th(BCLK-CS)
4ns.min
th(BCLK-DB)
4ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
th(BCLK-WR)
0ns.min