M16C62P_06 Datasheet, PDF (290/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
22.3 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial
programmer.
In CPU rewrite mode, only the user ROM area shown in Figure 22.1 can be rewritten. The boot ROM area cannot
be rewritten. Program and the block erase command are executed only in the user ROM area.
Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode. Table 22.3 lists
differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes.
Table 22.3 EW0 Mode and EW1 Mode
Item
Operating Mode
Space where the
rewrite control
program can be
placed
Space where the
rewrite control
program can be
executed
Space which can be
rewritten
Software Command
Restriction
Mode after Program
or Erasing
CPU State during
Auto Write and Auto
Erase
Flash Memory State
Detection
EW0 Mode
• Single-chip mod
• Memory expansion mode
• Boot mode
• User ROM area
• Boot ROM area
The rewrite control program must be
transferred to any space other than the
flash memory (e.g., RAM) before being
executed ⁽²⁾
User ROM area
None
Read status register mode
Operating
• Read the FMR00, FMR06 and FMR07
bits in the FMR0 register by program
• Execute the read status register
command to read the SR7, SR5 and
SR4 bits in the status register.
EW1 Mode
• Single-chip mode
• User ROM area
The rewrite control program can be
executed in the user ROM area
User ROM area
However, this excludes blocks with the
rewrite control program
• Program and block erase commands
cannot be executed in a block having
the rewrite control program.
• Erase all unlocked block command
cannot be executed when the lock bit
in a block having the rewrite control
program is set to “1” (unlocked) or
when the FMR02 bit in the FMR0
register is set to “1” (lock bit disabled).
• Read status register command cannot
be used.
Read array mode
Maintains hold state (I/O ports maintains
the state before the command was
executed) ⁽¹⁾
Read the FMR00, FMR06 and FMR07
bits in the FMR0 register by program
NOTES:
1. Do not generate an interrupt (except NMI interrupt) or DMA transfer.
2. 2. When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The
rewrite control program can only be executed in the internal RAM or in an external area that is
enabled for use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-
byte mode, the extended accessible area (40000h to BFFFFh) cannot be used.
Rev.2.41 Jan 10, 2006 Page 275 of 390
REJ09B0185-0241