M16C62P_06 Datasheet, PDF (140/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
13. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
WDC
000Fh
Bit Symbol
Bit Name
—
High-order Bit of Watchdog Timer
(b4-b0)
After Reset
00XXXXXXb⁽²⁾
Function
RW
RO
Cold Start / Warm Start Discrimination 0 : Cold Start
WDC5 _{Flag (1, 2)}
1 : Warm Start
RW
—
Reserved Bit
Set to “0”
(b6)
RW
Prescaler Select Bit
0 : Divided by 16
WDC7
1 : Divided by 128
RW
NOTES :
1. Writing to the WDC register factors the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less
than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice.
2. The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only.
Watchdog Timer Start Register ⁽¹⁾
b7
b0
Symbol
Address
After Reset
WDTS
000Eh
Indeterminate
Function
RW
The w atchdog timer is initialized and starts counting after a w rite instruction to this register.
The w atchdog timer value is alw ays initialized to “7FFFh” regardless of w hatever value is
WO
w ritten.
NOTES :
1. Write to the WDTS register after the w atchdog timer interrupt occurs.
Figure 13.2 WDC and WDTS Register
13.1 Count source protective mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer can be
kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit in the PM register to “1” results in the following conditions.
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
source.
Watchdog timer period =
Watchdog timer count (32768)
On-chip oscillator clock
• The CM10 bit in the CM1 register is disabled against write (Writing a “1” has no effect, nor is stop mode
entered).
• The watchdog timer does not stop when in wait mode or hold state.
Rev.2.41 Jan 10, 2006 Page 125 of 390
REJ09B0185-0241