M16C62P_06 Datasheet, PDF (236/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
(1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
(i=0 to 2)
Transfer clock
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RXDi
Trigger signal is applied to the TAjIN pin
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: Timer A3 when UART0; Timer A4 when UART1; Timer A0 when UART2
(2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit)
Transfer clock
TXDi
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
IR bit in UiBCNIC
register ⁽¹⁾
TE bit in UiC1
register
NOTES :
1. BCNIC register when UART2.
If ACSE bit = 1 (automatically
clear when bus collision occurs), the
TE bit is cleared to “0”
(transmission disabled) when the
IR bit in the UiBCNIC register= 1
(unmatching detected).
(3) The SSS Bit in the UiSMR Register (Transmit start condition select)
If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXDi
Transmission enable condition is met
If SSS bit = 1, the serial interface starts sending data at the rising edge ⁽¹⁾ of RXDi
CLKi
TXDi
(NOTE 2)
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
RXDi
NOTES :
1. The falling edge of RXDi when IOPOL=0; the rising edge of RXDi when IOPOL =1.
2. The transmit condition must be met before the falling edge ⁽¹⁾ of RXD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 17.33 Bus Collision Detect Function-Related Bits
Rev.2.41 Jan 10, 2006 Page 221 of 390
REJ09B0185-0241