M16C62P_06 Datasheet, PDF (308/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
22.3.8 Full Status Check
If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0
register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking
these bits (full status check).
Table 22.6 lists Errors and FMR0 Register State. Figure 22.14 shows a flow chart of the Full Status Check and
Handling Procedure for Each Error.
Table 22.6 Errors and FMR0 Register State
FMR00 Register
(Status Register) State
FMR07 bit FMR06 bit
Error
Error Occurrence Conditions
(SR5 bit) (SR4 bit)
Command
• Command is written incorrectly
1
1
Sequence error • A value other than “xxD0h” or “xxFFh” is written in the
second bus cycle of the lock bit program, block erase or
erase all unlocked block command ⁽¹⁾
Erase error
• The block erase command is executed on a locked block
1
0
• The block erase or erase all unlocked block command is
executed on an unlock block and auto erase operation is
not completed as expected ⁽²⁾
Program error • The program command is executed on locked blocks
• The program command is executed on unlocked blocks
0
1
but program operation is not completed as expected
• The lock bit program command is executed but program
operation is not completed as expected ⁽²⁾
NOTES:
1. The flash memory enters read array mode by writing command code “xxFFh” in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit is set to “1” (lock bit disabled), no error occurs even under the conditions
above.
Rev.2.41 Jan 10, 2006 Page 293 of 390
REJ09B0185-0241