M16C62P_06 Datasheet, PDF (216/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG count
source
RE bit in UiC1
register
RXDi
Transfer clock
RI bit in UiC1
register
RTSi
IR bit in SiRIC
register
“1”
“0”
Stop bit
Start bit
D0
D1 D7
Sampled “L”
Receive data taken in
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive
register to UiRB register
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 17.20 Receive Operation
17.1.2.1 Bit Rate
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table
17.9 lists Example of Bit Rates and Settings.
Table 17.9 Example of Bit Rates and Settings
Bit Rate
(bps)
Count Source
of UiBRG
1200
f8
Peripheral Function Clock : 16MHz
Set Value of
UiBRG : n
Bit Rate (bps)
103 (67h)
1202
2400
f8
51 (33h)
2404
4800
f8
25 (19h)
4808
9600
f1
103 (67h)
9615
14400
f1
68 (44h)
14493
19200
f1
51 (33h)
19231
28800
f1
34 (22h)
28571
31250
f1
31 (1Fh)
31250
38400
f1
25 (19h)
38462
51200
f1
19 (13h)
50000
Peripheral Function Clock : 24MHz
Set value of
UiBRG : n
155 (9Bh)
Bit Rate (bps)
1202
77 (4Dh)
2404
38 (26h)
4808
155 (9Bh)
9615
103 (67h)
14423
77 (4Dh)
19231
51 (33h)
28846
47 (2Fh)
31250
38 (26h)
38462
28 (1Ch)
51724
Rev.2.41 Jan 10, 2006 Page 201 of 390
REJ09B0185-0241