M16C62P_06 Datasheet, PDF (135/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.6 INT Interrupt
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi
bit in the IFSR register.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively. To use
the INT4 interrupt, set the IFSR6 bit in the IFSR register to “1” (= INT4). To use the INT5 interrupt, set the IFSR7
bit in the IFSR register to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested) before
enabling the interrupt.
Figure 12.11 shows the IFSR and IFSR2A Registers.
Interrupt Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
A ddres s
035Fh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
INT0 Interrupt Polarity Sw itching Bit 0 : One edge
IFSR0
1 : Both edges ⁽¹⁾
RW
INT1 Interrupt Polarity Sw itching Bit 0 : One edge
IFSR1
1 : Both edges ⁽¹⁾
RW
INT2 Interrupt Polarity Sw itching Bit 0 : One edge
IFSR2
1 : Both edges ⁽¹⁾
RW
INT3 Interrupt Polarity Sw itching Bit 0 : One edge
IFSR3
1 : Both edges ⁽¹⁾
RW
INT4 Interrupt Polarity Sw itching Bit 0 : One edge
IFSR4
1 : Both edges ⁽¹⁾
RW
INT5 Interrupt Polarity Sw itching Bit 0 : One edge
IFSR5
1 : Both edges ⁽¹⁾
RW
Interrupt Request Factor Select Bit ⁽²⁾ 0 : SI/O3 ⁽³⁾
IFSR6
_____
RW
1 : INT4
Interrupt Request Factor Select Bit ⁽²⁾ 0 : SI/O4 ⁽³⁾
IFSR7
_____
RW
1 : INT5
NOTES :
1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register are set to “0”
(= falling edge).
2. During memory expansion and microprocessor modes, w hen the data bus is 16 bits w ide (BYTE pin is "L"), set
this bit to “0” (= SI/O3, SI/O4).
3. When setting this bit to “0” (= SI/O3, SI/O4), make sure the POL bit in the S3IC and S4IC registers are set to “0”
(= falling edge).
Interrupt Factor Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Address
035Eh
After Reset
00XXXXXXb
Bit Symbol
Bit Name
Function
RW
— Nothing is assigned. When w rite, set to “0”.
(b5-b0) When read, their contents are indeterminate.
—
Interrupt Request Factor Select Bit ⁽¹⁾ 0 : Timer B3
IFSR26
1 : UART0 bus collision detection
RW
Interrupt Request Factor Select Bit ⁽²⁾ 0 : Timer B4
IFSR27
1 : UART1 bus collision detection
RW
NOTES :
1. Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using Timer B3
interrupt, clear the IFSR26 bit to “0” (Timer B3). When using UART0 bus collision detection, set the IFSR26 bit to “1”.
2. Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using Timer B4
interrupt, clear the IFSR27 bit to “0” (Timer B4). When using UART1 bus collision detection, set the IFSR27 bit to “1”.
Figure 12.11 IFSR and IFSR2A Registers
Rev.2.41 Jan 10, 2006 Page 120 of 390
REJ09B0185-0241