M16C62P_06 Datasheet, PDF (80/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
8.2.7 HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input
on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in process
finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during which time the
HLDA pin outputs a low-level signal.
Table 8.5 shows the Microcomputer Status in Hold State.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However, if the
CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate
accesses.
HOLD > DMAC > CPU
Figure 8.5 Bus-Using Priorities
Table 8.5 Microcomputer Status in Hold State
Item
BCLK
Output
Status
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH, ^{High-impedance}
WR, BHE
I/O ports
P0, P1, P3, P4 ⁽²⁾ High-impedance
P6 to P14 ⁽¹⁾
Maintains status when HOLD signal is received
HLDA
Internal Peripheral Circuits
ALE Signal
Output “L”
ON (but watchdog timer stops)⁽³⁾
Undefined
NOTES:
1. P11 to P14 are included in the 128-pin version.
2. When I/O port function is selected.
3. The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to “1” (the count
source for the watchdog timer is the on-chip oscillator clock).
8.2.8 8.2.8 BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that of the
CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 CPU Clock and Peripheral Function Clock.
Rev.2.41 Jan 10, 2006 Page 65 of 390
REJ09B0185-0241