M16C62P_06 Datasheet, PDF (114/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
10.4.3.3 Exiting Stop Mode
Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function
interrupt.
When the hardware reset, NMI interrupt or low voltage detection interrupt is used to exit stop mode, set all
ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to “000b” (interrupt
disabled) before setting the CM10 bit to “1”.
When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to “1” after the following
settings are completed.
(1) Set the ILVL2 to ILVL0 bits in the interrupt control registers to decide the peripheral priority level of
the peripheral function interrupt.
Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to “0” by setting the
all ILVL2 to ILVL0 bits to “000b”.
(2) Set the I flag to “1”.
(3) Start operation of peripheral function being used to exit wait mode.
When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when an
interrupt request is generated and the CPU clock is supplied again.
When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is as
follows, in accordance with the CPU clock source setting before the microcomputer had entered stop mode.
• When the sub clock is the CPU clock before entering stop mode : Sub clock
• When the main clock is the CPU clock source before entering stop mode : Main clock divided by 8
• When the on-chip oscillator clock is the CPU clock source before entering stop mode
: On-chip oscillator clock divided by 8
Figure 10.10 shows the State Transition from Normal Operating Mode to Stop Mode and Wait Mode. Figure
10.11 shows the State Transition in Normal Operating Mode.
Table 10.8 shows a state transition matrix describing Allowed Transition and Setting. The vertical line shows
current state and horizontal line shows state after transition.
Reset
All oscillators stopped
Stop mode
CM10=1⁽⁶⁾
Interrupt
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1⁽⁵⁾
Interrupt
Stop mode
CM10=1⁽⁶⁾
Stop mode
CM10=1⁽⁶⁾
Interrupt
When
low power
dissipation
mode
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
When
low-
speed
mode
(NOTES 1, 2)
PLL operation
mode
Low-speed, low power
dissipation mode
Stop mode
CM10=1⁽⁶⁾
Interrupt(4)
On-chip oscillator, On-chip
oscillator dissipation mode
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
Normal mode
CPU operation stopped
Wait mode
Wait mode
Wait mode
Wait mode
NOTES :
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. Shown above is the case where the PM21 bit in the PM2 register = 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 and CM1 registers per 16 bit with CM21=0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to “ 0” (oscillation stop and oscillation restart detection function disabled).
Figure 10.10 State Transition to Stop Mode and Wait Mode
Rev.2.41 Jan 10, 2006 Page 99 of 390
REJ09B0185-0241