M16C62P_06 Datasheet, PDF (81/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
Table 8.6 Pin Functions for Each Processor Mode
Processor Mode
PM05 to PM04 bits
Data Bus Width BYTE
Pin
P0_0 to P0_7
P1_0 to P1_7
P2_0
P2_1 to P2_7
P3_0
P3_1 to P3_3
P3_4 to
P3_7
PM11=0
PM11=1
P4_0 to
P4_3
PM06=0
PM06=1
P4_4
CS0=0
CS0=1
P4_5
CS1=0
CS1=1
P4_6
CS2=0
CS2=1
P4_7
CS3=0
CS3=1
P5_0
PM02=0
PM02=1
P5_1
PM02=0
PM02=1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
Memory Expansion Mode or Microprocessor Mode
Memory
Expansion Mode
00b(separate bus) bits
01b(CS2 is for multiplexed bus and
others are for separate bus)
10b(CS1 is for multiplexed bus and
others are for separate bus)
11b (multiplexed
bus for the entire
space) ⁽¹⁾
8 bits
“H”
D0 to D7
I/O ports
A0
16 bits
“L”
D0 to D7
D8 to D15
A0
8 bits
“H”
D0 to D7 ⁽⁴⁾
I/O ports
A0/D0 ⁽²⁾
16 bits
“L”
D0 to D7 ⁽⁴⁾
D8 to D15 ⁽⁴⁾
A0
8 bits
“H”
I/O ports
I/O ports
A0/D0
A1 to A7
A8
A1 to A7
A8
A1 to A7
/D1 to D7 ⁽²⁾
A8
A1 to A7
/D0 to D6 ⁽²⁾
A8/D7 ⁽²⁾
A1 to A7
/D1 to D7
A8
A9 to A11
I/O ports
A12 to A15
I/O ports
I/O ports
A16 to A19
I/O ports
I/O ports
I/O ports
CS0
I/O ports
CS1
I/O ports
CS2
I/O ports
CS3
WR
− ⁽³⁾
WRL
− ⁽³⁾
WRL
− ⁽³⁾
BHE
− ⁽³⁾
WRH
− ⁽³⁾
WRH
− ⁽³⁾
RD
BCLK
HLDA
HOLD
ALE
RDY
I/O ports : Function as I/O ports or peripheral function I/O pins.
NOTES:
1. To set the PM01 to PM00 bits are set to “01b” and the PM05 to PM04 bits are set to “11b” (multiplexed bus
assigned to the entire CS space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS
pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “11b” after reset. If the PM05 to PM04 bits are
set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case
the accessible area for each CS is 256 bytes.
2. In separate bus mode, these pins serve as the address bus.
3. If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).
4. When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.
Rev.2.41 Jan 10, 2006 Page 66 of 390
REJ09B0185-0241