M16C62P_06 Datasheet, PDF (100/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
System Clock Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol
CM1
Address
0007h
After Reset
00100000b
Bit Symbol
Bit Name
Function
RW
All Clock Stop Control Bit ^{(4, 6)}
0 : Clock on
CM10
1 : All clocks off (stop mode)
RW
System Clock Select Bit 1 ^{(6, 7)}
0 : Main clock
CM11
1 : PLL clock ⁽⁵⁾
RW
—
Reserved Bit
Set to “0”
(b4-b2)
RW
XIN-XOUT Drive Capacity
0 : LOW
CM15 _{Select Bit (2)}
1 : HIGH
RW
Main Clock Division Select Bit 1 ⁽³⁾ b7 b6
CM16
0 0 : No division mode
RW
0 1 : Divide-by-2 mode
CM17
1 0 : Divide-by-4 mode
RW
1 1 : Divide-by-16 mode
NOTES :
1. Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When entering stop mode from high-speed or middle-speed mode, or the CM05 bit is set to “1” (main clock stops) in
low speed mode, the CM15 bit is set to “1” (drive capacity high).
3. This bit is valid w hen the CM06 bit is set to “0” (CM16 and CM17 bits enabled).
4. If the CM10 bit is set to “1” (stop mode), XOUT is held “H” and the internal feedback resistor is disconnected. The
XCIN and XCOUT pins are in high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the
CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), w ait tsu (PLL) elapses before setting the CM11
bit to “1” (PLL clock).
6. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM10, CM11 bits.
When the PM22 bit in the PM2 register is set to “1” (on-chip oscillator clock is selected as w atchdog timer count
source), this bit remains unchanged even if w riting to the CM10 bit.
7. This bit is valid w hen the CM07 bit is set to “0” and the CM21 bit is set to “0”.
Figure 10.3 CM1 Register
Rev.2.41 Jan 10, 2006 Page 85 of 390
REJ09B0185-0241