M16C62P_06 Datasheet, PDF (230/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
17.1.4 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable.
Table 17.15 lists the Special Mode 2 Specifications. Table 17.16 lists the Registers to Be Used and Settings in
Special Mode 2. Figure 17.29 shows Serial Bus Communication Control Example (UART2).
Table 17.15 Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
Transfer data length: 8 bits
• Master mode
CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• Slave mode
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Controlled by input/output ports
Before transmission can start, meet the following requirements ⁽¹⁾
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register = 0 (data present in UiTB register)
Before reception can start, meet the following requirements ⁽¹⁾
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data from
the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Overrun error ⁽²⁾
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the
receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
not change.
Rev.2.41 Jan 10, 2006 Page 215 of 390
REJ09B0185-0241