M16C62P_06 Datasheet, PDF (381/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
24.7 Interrupt
24.7.1 Reading address 00000h
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads
interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the
interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is cleared to “0”. This factors a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
24.7.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to “0000h” after
reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the program may go
out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first and
only the first instruction after reset, all interrupts including NMI interrupt are disabled.
24.7.3 The NMI Interrupt
• The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC1 via a
resistor (pull-up).
• The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the P8_5
bit can only be read when determining the pin level in NMI interrupt routine.
• Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
• Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin goes
low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip does not
drop. In this case, normal condition is restored by an interrupt generated thereafter.
• The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles + 300
ns or more.
Rev.2.41 Jan 10, 2006 Page 366 of 390
REJ09B0185-0241