M16C62P_06 Datasheet, PDF (74/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
8. Bus
Note
The M16C/62P (80-pin version) and M16C/62PT do not use bus control pins.
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/
output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/
WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
8.1 Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0 register.
Table 8.1 shows the Difference Between a Separate Bus and Multiplexed Bus.
8.1.1 Separate Bus
In this bus mode, data and address are separate.
8.1.2 Multiplexed Bus
In this bus mode, data and address are multiplexed.
8.1.2.1 When the input level on BYTE pin is high (8-bit data bus)
D0 to D7 and A0 to A7 are multiplexed.
8.1.2.2 When the input level on BYTE pin is low (16-bit data bus)
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External devices
connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd
addresses cannot be accessed.
Table 8.1 Difference Between a Separate Bus and Multiplexed Bus
Pin Name ⁽¹⁾
P0_0 to P0_7/D0 to D7
Separate Bus
D0 to D7
Multiplex Bus
BYTE = H
BYTE = L
(NOTE 2)
(NOTE 2)
P1_0 to P1_7/D8 to D15
P2_0/A0 (/D0/-)
P2_1 to P2_7/A1 to A7
(/D1 to D7/D0 to D6)
P3_0/A8 (/-/D7)
D8 to D15
A0
A1 to A7
A8
I/O Port
P1_0 to P1_7
A0
D0
A1 to A7 D1 to D7
A8
(NOTE 2)
A0
A1 to A7 D0 to D6
A8
D7
NOTES:
1. See Table 8.6 Pin Functions for Each Processor Mode for bus control signals other than the
above. Setting Processor Modes.
2. It changes with a setup of PM05 to PM04, and area to access.
See Table 8.6 Pin Functions for Each Processor Mode for details.
Rev.2.41 Jan 10, 2006 Page 59 of 390
REJ09B0185-0241