M16C62P_06 Datasheet, PDF (103/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
PLL Control Register 0 ^{(1, 2)}
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol
PLC0
Address
001Ch
After Reset
0001X010b
Bit Symbol
Bit Name
Function
RW
PLL Multiplying Factor
b2 b1 b0
PLC00 ^{Select Bit (3)}
0 0 0 : Do not set
RW
0 0 1 : Multiply by 2
0 1 0 : Multiply by 4
PLC01
0 1 1 : Multiply by 6
RW
1 0 0 : Multiply by 8
PLC02
101:
1 1 0 : Do not set
111:
RW
—
Nothing is assigned. When w rite, set to “0”.
(b3) When read, its content is indeterminate.
—
—
Reserved Bit
Set to “1”
(b4)
RW
—
Reserved Bit
Set to “0”
(b6-b5)
RW
Operation Enable Bit ⁽⁴⁾
0: PLL Off
PLC07
1: PLL On
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When the PM21 bit in the PM2 register is “1” (clock modification disable), w riting to this register has no effect.
3. These three bits can only be modified w hen the PLC07 bit = 0 (PLL turned off). The value once w ritten to this bit
cannot be modified.
4. Before setting this bit to “1”, set the CM07 bit in the CM0 register to “0” (main clock), set the CM17 to CM16 bits in the
CM1 register to “00b” (main clock undivided mode), and set the CM06 bit in the CM0 register to “0” (CM16 and CM17
bits enable).
Figure 10.6 PLC0 Register
Rev.2.41 Jan 10, 2006 Page 88 of 390
REJ09B0185-0241