M16C62P_06 Datasheet, PDF (165/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
15.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-phase
pulse signal processing.
This function can only be used in Timer A3 event counter mode during two-phase pulse signal processing, free-
running type, x4 processing, with Z-phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing “0000h” to the TA3 register and setting the TAZIE
bit in the ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the
rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width applied to the INT2
pin must be equal to or greater than one clock cycle of Timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 15.11 shows the
Relationship Between the Two-Phase Pulse (A phase and B phase) and the Z-Phase.
If Timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a Timer A3
interrupt request is generated twice in succession. Do not use Timer A3 interrupt when using this function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
ZP ⁽¹⁾
Timer A3
Input equal to or greater than one clock cycle
of count source
m m+1 1
2
3
4
5
NOTES :
1. This timing diagram is for the case where the POL bit in the INT2IC register = 1 (= rising edge).
Figure 15.11 Two-Phase Pulse (A phase and B phase) and the Z-Phase
Rev.2.41 Jan 10, 2006 Page 150 of 390
REJ09B0185-0241