M16C62P_06 Datasheet, PDF (251/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
A/D Control Register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
ADCON2
03D4h
00h
Bit Symbol
Bit Name
Function
RW
A/D Conversion Method Select 0 : Without sample and hold
SMP _Bit
1 : With sample and hold
RW
A/D Input Group Select Bit
b2 b1
ADGSEL0
0 0 : Port P10 group is selected
RW
0 1 : Do not set
ADGSEL1
1 0 : Port P0 group is selected ⁽²⁾
1 1 : Port P2 group is selected
RW
—
Reserved Bit
Set to “0”
(b3)
RW
Frequency Select Bit 2 ⁽³⁾
0: Selects fAD, fAD divided by 2, or fAD
CKS2
divided by 4.
1: Selects fAD divided by 3, fAD divided
RW
by 6, or fAD divided by 12.
—
Nothing is assigned.
(b7-b5) When w rite, set to “0”. When read, their contents are “0”.
—
NOTES :
1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
2. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. The ØAD frequency must be 12 MHz or less. The selected ØAD frequency is determined by a combination of the CKS0
bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
0
0
0
0
1
1
1
1
CKS1
0
0
1
1
0
0
1
1
CKS0
0
1
0
1
0
1
0
1
ØAD
Divide-by-4 of fAD
Divide-by-2 of fAD
fAD
Ddivide-by-12 of fAD
Divide-by-6 of fAD
Divide-by-3 of fAD
Figure 18.3 ADCON2 Register
Rev.2.41 Jan 10, 2006 Page 236 of 390
REJ09B0185-0241