M16C62P_06 Datasheet, PDF (109/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
10.4 Power Control
Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode
states, except wait mode and stop mode, are called normal operating mode in this document.
10.4.1 Normal Operating Mode
Normal operating mode is further classified into seven modes.
In normal operating mode, because the CPU clock and the peripheral function clocks both are on, the CPU and
the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The
higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the
smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must
be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a sufficient wait
time in a program until it becomes oscillating stably.
Note that operating modes cannot be changed directly from low speed or low power dissipation mode to on-
chip oscillator or on-chip oscillator low power dissipation mode. Nor can operating modes be changed directly
from on-chip oscillator or on-chip oscillator low power dissipation mode to low speed or low power dissipation
mode. Where the CPU clock source is changed from the on-chip oscillator to the main clock, change the
operating mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit
in the CM0 register was set to “1”) in the on-chip oscillator mode.
10.4.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count
source for Timers A and B.
10.4.1.2 PLL Operating Mode
The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU clock.
If the sub clock is on, fC32 can be used as the count source for Timers A and B. PLL operating mode can be
entered from high speed mode. If PLL operating mode is to be changed to wait or stop mode, first go to high
speed mode before changing.
10.4.1.3 Medium-Speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for Timers A and B.
10.4.1.4 Low-Speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral function
clock when the CM21 bit in the CM2 register is set to “0” (on-chip oscillator turned off), and the on-chip
oscillator clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for Timers A and B.
10.4.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the
CPU clock. The fC32 clock can be used as the count source for Timers A and B.
Simultaneously when this mode is selected, the CM06 bit becomes “1” (divided by 8 mode). In the low power
dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by 8) mode is to be
selected when the main clock is operated next
10.4.1.6 On-chip Oscillator Mode
The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be
used as the count source for Timers A and B. When the operating mode is returned to the high and medium
speed modes, set the CM06 bit in the CM0 register to “1” (divided by 8 mode).
Rev.2.41 Jan 10, 2006 Page 94 of 390
REJ09B0185-0241