M16C62P_06 Datasheet, PDF (178/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol
Address
After Reset
TB0MR to TB2MR 039Bh to 039Dh
00XX0000b
TB3MR to TB5MR 035Bh to 035Dh
00XX0000b
Bit Symbol
Bit Name
Function
RW
TMOD0 Operation Mode Select Bit b1 b0
RW
TMOD1
1 0 : Pulse period / pulse w idth measurement
mode
RW
Measurement Mode Select b3 b2
Bit
0 0 : Pulse period measurement
(Measurement betw een a falling edge and
MR0
the next falling edge of measured pulse)
RW
0 1 : Pulse period measurement
(Measurement betw een a rising edge and
the next rising edge of measured pulse)
1 0 : Pulse w idth measurement
(Measurement betw een a falling edge and
the next rising edge of measured pulse
MR1
and betw een a rising edge and the next
RW
falling edge)
1 1 : Do not set to this value
TB0MR, TB3MR registers
Set to “0” in pulse period and pulse w idth measurement mode
RW
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to “0”.
—
When read, its content is indeterminate.
Timer Bi Overflow Flag ⁽¹⁾ 0 : Timer did not overflow
MR3
1 : Timer has overflow ed
RO
Count Source Select Bit b7 b6
TCK0
0 0 : f1 or f2 ⁽²⁾
RW
0 1 : f8
TCK1
1 0 : f32
RW
1 1 : fC32
NOTES :
1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow )
by w riting to the TBiMR register at the next count timing or later after the MR3 bit w as set to “1” (overflow ed). The
MR3 bit cannot be set to “1” in a program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR
register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
2. Selected by PCLK0 bit in the PCLKR register.
Figure 15.21 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.2.41 Jan 10, 2006 Page 163 of 390
REJ09B0185-0241