M16C62P_06 Datasheet, PDF (183/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Three-Phase Control Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
INVC1
0349h
00h
Bit Symbol
Bit Name
Function
RW
Timer A1, A2 and A4 Start 0 : Timer B2 underflow
INV10 _{Trigger Select Bit}
1 : Timer B2 underflow and w rite to Timer B2
RW
Timer A1-1, A2-1 and A4-1 0 : Three-phase mode 0
INV11 _{Control Bit (2, 3)}
1 : Three-phase mode 1
RW
Dead Time Timer Count 0 : f1 or f2
INV12 _{Source Select Bit}
1 : f1 divided-by-2 or f2 divided-by-2
RW
Carrier Wave Detect Bit ⁽⁴⁾ 0 : Timer A1 reload control signal is “0”
INV13
1 : Timer A1 reload control signal is “1”
RO
Output Polarity Control Bit 0 : Active “L” of an output w aveform
INV14
1 : Active “H” of an output w aveform
RW
Dead Time Disable Bit
0 : Enables dead time
INV15
1 : Disables dead time
RW
Dead Time Timer Trigger 0 : Falling edge of a one-shot pulse of Timer A1,
Select Bit
INV16
A2, A4 ⁽⁵⁾
1 : Rising edge of the three-phase output shift
RW
register (U-, V-, W-phase)
—
Reserved Bit
Set to “0”
(b7)
RW
NOTES :
1. Rew rite the INVC1 register after the PRC1 bit in the PRCR register is set to “1” (w rite enable).
The timers A1, A2, A4, and B2 must be stopped during rew rite.
2. The follow ing table lists how the INV11 bit w orks.
Item
INV11=0
INV11=1
Mode
Three-phase mode 0
Three-phase mode 1
TA11, TA21 and TA41
Registers
Not used
Used
INV00 and INV01 Bit
Disabled.
The ICTB2 counter is incremented
w henever Timer B2 underflow s
Enabled
INV13 Bit
Disabled
Enabled w hen INV11=1 and INV06=0
3. When the INV06 bit is set to “1” (saw tooth w ave modulation mode), set the INV11 bit to “0” (three-phase mode 0).
Also, w hen the INV11 bit is set to “0”, set the PWCON bit in the TB2SC register to “0” (Timer B2 is reloaded w hen
Timer B2 underflow s).
4. The INV13 bit is enabled only w hen the INV06 bit is set to “0” (Triangular w ave modulation mode) and the INV11 bit to
“1” (three-phase mode 1).
5. If the follow ing conditions are all met, set the INV16 bit to “1” (rising edge of the three-phase output shift register).
• The INV15 bit is set to “0” (dead time timer enabled)
• The Dij bit (i=U, V or W, j=0, 1) and DiBj bit alw ays have different values w hen the INV03 bit is set to “1”.
(The positive-phase and negative-phase alw ays output opposite level signals.)
If above conditions are not met, set the INV16 bit to “0” (falling edge of a one-shot pulse of Timer A1, A2, A4).
Figure 16.3 INVC1 Register
Rev.2.41 Jan 10, 2006 Page 168 of 390
REJ09B0185-0241