M16C62P_06 Datasheet, PDF (121/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12. Interrupt
Note
The M16C/62P (80-pin version) do not use INT3 to INT5 interrupt of peripheral function.
The M16C/62PT (100-pin version) do not use low voltage detection interrupt.
The M16C/62PT (80-pin version) do not use low voltage detection interrupt and INT3 to INT5 interrupt of peripheral
function.
12.1 Type of Interrupts
Figure 12.1 shows Type of Interrupts.
Software
(Non-maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Interrupt
Hardware
Special
(Non-maskable interrupt)
NMI
DBC ⁽²⁾
Watchdog timer
Oscillation stop and re-oscillation
detection
Low voltage detection
Single step ⁽²⁾
Address match
Peripheral function ⁽¹⁾
(Maskable interrupt)
NOTES:
1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.
2. Do not normally use this interrupt because it is provided exclusively for use by development tools.
Figure 12.1 Type of Interrupts
• Maskable Interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-Maskable Interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag)
or whose interrupt priority cannot be changed by priority level.
Rev.2.41 Jan 10, 2006 Page 106 of 390
REJ09B0185-0241