M16C62P_06 Datasheet, PDF (185/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
16. Three-Phase Motor Control Timer Function
Timer B2 Special Mode Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TB2SC
039Eh
XXXXXX00b
Bit Symbol
Bit Name
Function
RW
Timer B2 Reload Timing
0 : Timer B2 underflow
PWCOM ^{Sw itching Bit}
1 : Timer A output at odd-numbered
RW
occurrences ⁽²⁾
____
Three Phase Output Port NMI
____
0 : Three-phase output forcible cutoff by NMI
Control Bit 1(3)
IVPCR1
input (high-impedance) disabled
____
RW
1 : Three-phase output forcible cutoff by NMI
input (high-impedance) enabled
— Nothing is assigned. When w rite, set to “0”.
(b7-b2) When read, their contents are indeterminate.
—
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. If the INV11 bit is “0” (three-phase mode 0) or the INV06 bit is “1” (saw tooth w ave modulation mode), set this bit to “0” (Timer
B2 underflow ).
__
__
3. Related pins are U(P8_0/TA4OUT), U(P8_1/TA4IN), V(P7_2/CLK2/TA1OUT), V(P7_3/CTS2/RTS2/TA1IN),
___
____
W(P7_4/TA2OUT), W(P7_5/TA2IN). If a low -level signal is applied to the NMI
pin w hen the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of w hich functions of those pins are
____
being used. After forced interrupt (cutoff), input “H” to the NMI pin and set IVPCR1 bit to “0”: this forced cutoff w ill be reset.
Three-Phase Output Buffer Register i ⁽¹⁾ (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
Address
After Reset
IDB0, IDB1
034Ah, 034Bh
00h
Bit Symbol
Bit Name
Function
RW
U-Phase Output Buffer i Write output level
DUi
0 : Active level
RW
DUBi
__
U-Phase Output Buffer i
1 : Inactive level
RW
V-Phase Output Buffer i ^{When read, the value of the three-phase shift}
DVi
register is read.
RW
__
DVBi ^{V-Phase Output Buffer i}
RW
W-Phase Output Buffer i
DWi
RW
__
DWBi ^{W-Phase Output Buffer i}
RW
—
Reserved Bit
Set to “0”
(b7-b6)
RO
NOTES :
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger.
After the transfer trigger occurs, the values w ritten in the IDB0 register determine each phase output signal first.
Then the value w ritten in the IDB1 register on the falling edge of Timers A1, A2 and A4 one-shot pulse determines
each phase output signal.
Figure 16.5 TB2SC, IDB0 and IDB1 Registers
Rev.2.41 Jan 10, 2006 Page 170 of 390
REJ09B0185-0241