M16C62P_06 Datasheet, PDF (84/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
Table 8.8 Bit and Bus Cycle Related to Software Wait
Area
SFR
Internal
RAM,
ROM
External
Area
Bus Mode
−
−
−
−
Separate
Bus
PM2
PM1
Register Register
PM20 Bit PM17 Bit ⁽⁵⁾
1
−
0
−
−
0
−
1
−
0
CSR Register
CS3W Bit ⁽¹⁾
CS2W Bit ⁽¹⁾
CS1W Bit ⁽¹⁾
CS0W Bit ⁽¹⁾
−
−
−
−
1
CSE Register
CSE31W to CSE30W Bit
CSE21W to CSE20W Bit
CSE11W to CSE10W Bit
CSE01W to CSE00W Bit
−
−
−
−
00b
−
−
0
00b
−
−
0
01b
−
−
0
10b
−
1
0
00b
Multiplexed
−
−
0
00b
Bus ⁽²⁾
−
−
0
01b
−
−
0
10b
−
1
0
00b
Software
Wait
Bus Cycle
−
−
No wait
1 wait
2 BCLK cycles ⁽³⁾
3 BCLK cycles ⁽³⁾
1 BCLK cycle ⁽⁴⁾
2 BCLK cycles
No wait
1 wait
2 waits
3 waits
1 wait
1 wait
2 waits
3 waits
1 wait
1 BCLK cycle
(read)
2 BCLK cycles
(write)
2 BCLK cycle ⁽⁴⁾
3 BCLK cycles
4 BCLK cycle
2 BCLK cycle
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
NOTES:
1. To use the RDY signal, set this bit to “0”.
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait
state).
3. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by
the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the
PM20 bit to “0” (2 wait cycles).
4. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0”
(with wait state), and the CSE register is set to “00h” (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
5. When PM17 bit is set to “1” and accesses an external area, set the CSiW (i=0 to 3) bits to “0” (with
wait state).
Rev.2.41 Jan 10, 2006 Page 69 of 390
REJ09B0185-0241