M16C62P_06 Datasheet, PDF (233/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
17.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the
UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 17.30 shows the Transmission and Reception Timing in Master Mode (Internal Clock).
Figure 17.31 shows the Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) while
Figure 17.32 shows the Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock).
Clock output
“H”
(CKPOL=0, CKPH=0) _{“L”}
Clock output
“H”
(CKPOL=1, CKPH=0) _{“L”}
Clock output
“H”
(CKPOL=0, CKPH=1) _{“L”}
Clock output
“H”
(CKPOL=1, CKPH=1) _{“L”}
Data output timing ^{“H”}
“L”
Data input timing
D0 D1 D2 D3 D4 D5 D6 D7
Figure 17.30 Transmission and Reception Timing in Master Mode (Internal Clock)
Rev.2.41 Jan 10, 2006 Page 218 of 390
REJ09B0185-0241