M16C62P_06 Datasheet, PDF (154/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
15.1 Timer A
Note
The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN and TA1OUT pins
of Timer A1, and TA2IN and TA2OUT pins of Timer A2.
[Precautions when using Timer A1 and Timer A2]
• Timer Mode
The Gate Function and the Pulse Output Function cannot be used. Set the MR2 to
MR0 bits in the TA1MR and TA2MR registers to “000b” when using Timer
Mode.
• Event Counter Mode The Pulse Output Function cannot be used and external input signals cannot be counted.
Two-phase Pulse Signal of Timer A2 cannot be used. Set the MR2 to MR0 bits in the
TA1MR and TA2MR registers to “000b” when using the Event Counter Mode.
• One-shot Timer Mode The Pulse Output Function cannot be used and count start by the external trigger cannot
be counted. Set the MR1 to MR0 bits in the TA1MR and TA2MR registers to “00b”
when using the One-shot Timer Mode.
• Pulse Width
PWM pulse cannot be outputted.
Modulation Mode
Figure 15.3 shows a Timer A Block Diagram. Figures 15.4 to 15.7 show registers related to Timer A. Timer A
supports the following four modes. Except in event counter mode, Timers A0 to A4 all have the same function. Use
the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer Mode:
The timer counts an internal count source.
• Event Counter Mode:
The timer counts pulses from an external device or overflows and
underflows of other timers.
• One-shot Timer Mode:
The timer outputs a pulse only once before it reaches the minimum
count “0000h”.
• Pulse Width Modulation (PWM) Mode: The timer outputs pulses in a given width successively.
Select clock
High-Order Bits of Data Bus
Select Count Source
· Timer
· One-Shot Timer
:TMOD1 to TMOD0=00, MR2=0
:TMOD1 to TMOD0=10
f1 or f2 ⁰⁰
· Pulse Width Modulation :TMOD1 to TMOD0=11 _{TMOD1 to TMOD0,}
f8 ⁰¹
MR2
f32 ¹⁰
fC32 ¹¹
· Timer (gate function): TMOD1 to TMOD0=00,
MR2=1
Low-Order Bits of Data Bus
8 low-order
bits
8 high-
order bits
Reload Register
TCK1 to TCK0
· Event counter :TMOD1 to TMOD0=01
Polarity
Selector
TAiIN
00
TB2 Overflow ^{(1) 01}
TAj Overflow ^{(1) 10}
TAk Overflow ^{(1) 11}
TAiS
To external
trigger circuit
00
01
11
Decrement
01
Counter
Increment / decrement
Always decrement except
in event counter mode
TAiTGH to TAiTGL
TAiUD
0
TMOD1 to TMOD0
1
TAiOUT
Pulse Output
i=0 to 4
j=i-1, however, j=4 if i=0
k=i+1, however, k=0 if i=4
NOTES:
1. Overflow or underflow
MR2
Toggle Flip Flop
TAi
Addresses
Timer A0 0387h - 0386h
Timer A1 0389h - 0388h
Timer A2 038Bh - 038Ah
Timer A3 038Dh - 038Ch
Timer A4 038Fh - 038Eh
TAj
TAk
Timer A4 Timer A1
Timer A0 Timer A2
Timer A1 Timer A3
Timer A2 Timer A4
Timer A3 Timer A0
TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register
TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4
TAiS : Bits in the TABSR register
TAiUD : Bits in the UDF register
Figure 15.3 Timer A Block Diagram
Rev.2.41 Jan 10, 2006 Page 139 of 390
REJ09B0185-0241